FIG. 3 is a block diagram of a hardware accelerator in accordance with an embodiment of the present invention.
FIG. 4 is a block diagram of a controller in accordance with an embodiment of the present invention.
FIG. 5 is a diagram illustrating the execution flow of a given data operation in accordance with an embodiment of the present invention.
FIG. 6 is a flowchart of a method for performing a computation task using a hardware accelerator in accordance with an embodiment of the present invention.
FIG. 7 is a flowchart of a method for creating replication units in accordance with an embodiment of the present invention.
FIG. 8 is a flowchart of a method for executing a computation task composed of a set of operations in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION
The descriptions of the various embodiments of the present invention will be presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
