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Hardware accelerator for executing a computation task

專利號
US11175957B1
公開日期
2021-11-16
申請人
International Business Machines Corporation（US NY Armonk）
發(fā)明人
Dionysios Diamantopoulos; Florian Michael Scheidegger; Adelmo Cristiano Innocenza Malossi; Christoph Hagleitner; Konstantinos Bekas
IPC分類
G06F9/30; G06F9/50; G06F9/38
技術領域
bit,may,unit,input,be,units,data,operands,tensor,hardware
地域： NY NY Armonk

摘要

The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.

說明書

FIG. 7 is a flowchart of a method for creating replication units in accordance with an embodiment of the present invention. The method of FIG. 7 may for example be performed by an automatic generator 700 using a FPGA 710. The FPGA 710 may comprise a controller and first computation unit that can perform data operations with a full precision, e.g., 8-bit.

權利要求

1
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