Hardware accelerator for executing a computation task
地域：
NY
NY Armonk
摘要
The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.
說明書
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The computation task may be any task that is composed of operations that may be performed by the hardware accelerator. The set of operations may be basic computations that can be performed by the hardware accelerator. Each operation of the set of operations may, for example, comprise a multiplication operation, addition operation, or another operation such as an Open Neural Network Exchange (ONNX) operation or a Neural Network Exchange Format (NNEF) operation. The computation task may, for example, be a training or inference of a neural network. The set of operations may be tensor-operations, such as blocked-matrix operations and multi-dimensional convolutions.
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