The input data may, for example, comprise operands of the data operation. In case the data operation is a multiplication operation, the operands of the input data may be two operands. The controller may be configured to select the computation unit by, for example, calculating the maximum number of leading zeros that is present in both operands of the input data. The calculated number of leading zeros is indicative of a highest bit length that can be used to perform the operation faster without losing in accuracy. For example, if the number of calculated leading zeros is L and the highest bit length that is processed by the controller is n-bit, the selected computation unit may be associated with a bit length k-bit, wherein k≥n?L and k≤n. This may be advantageous as it may be implemented using a simplistic design of comparators (e.g., only logic gates may be used in the controller). Thus, the area and latency overhead of the controller may be small. The controller may be able to quickly decide which of the computation units can deliver valid results without overfloats.

According to one embodiment, the controller is configured to stop execution of the operation by the non-selected computation unit(s). The controller may be configured to generate control signals or commands to the set of computation units and other units of the hardware accelerator. For example, the set of computation units comprises N computation units, where N≥2. The controller is configured to stop execution of the operation by the non-selected N?1 computation units. For example, as soon as the controller makes a decision, the results of the selected computation unit are forwarded, and all the rest speculated execution may be forced to cancel the calculation.