Soft-decision input generation for data storage systems
地域：
CA
CA San Jose
摘要
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
說明書
This application is a continuation of application Ser. No. 16/112,429, filed on Aug. 24, 2018, now U.S. Pat. No. 10,635,524, which is a continuation of application Ser. No. 13/797,943, filed on Mar. 12, 2013, now U.S. Pat. No. 10,061,640, the entirety of each of which is incorporated herein by reference for all purposes.
This disclosure relates to data storage systems. More particularly, the disclosure relates to systems and methods for generating log-likelihood ratios for data storage systems.
Soft-decision low-density parity-check code (LDPC) error code correction (ECC) can improve the reliability of a data storage system and reduce the number of data errors. Log-likelihood ratios (LLRs) are commonly used as the inputs for soft-decision LDPC engines. Data storage systems that use flash memories (e.g., NAND) as data storage media can use LLR calculations for reading memory cells when LDPC based on single read input is insufficient to decode the originally-stored data.
Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of the inventions. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure. Throughout the drawings, reference numbers may be reused to indicate correspondence between reference elements.
權(quán)利要求
What is claimed is:1. A computer-implemented method, comprising:obtaining a first data stored in a first memory location of a memory; generating read values, based on a plurality of reads performed on the first data; computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and when one or more second memory locations of the memory are physically located within a target value,selecting one or more LLRs from the plurality of LLRs; and decoding data stored in the one or more second memory locations using the selected one or more LLRs. 2. The computer-implemented method of claim 1 , whereinthe target value is a target proximity value, wherein the computer-implemented method comprises: obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations, and wherein selecting the one or more LLRs comprises selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics. 3. The computer-implemented method of claim 1 , whereinthe read values are correlated with the first data. 4. The computer-implemented method of claim 1 , comprising: placing the plurality of LLRs into a data structure associated with the first memory location. 5. The computer-implemented method of claim 4 , comprising: periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations. 6. The computer-implemented method of claim 1 , comprising:determining whether data in a third memory location is successfully decoded using a first read voltage; and when the third memory location is not successfully decoded using the first read voltage:decoding data in a fourth memory location using the first read voltage; and when the data in the fourth memory location is successfully decoded using the first read voltage:treating the data in the fourth memory location as the first data. 7. The computer-implemented method of claim 6 , comprising: when the third memory location is successfully decoded using the first read voltage, treating the data in the third memory location as the first data. 8. A data storage system, comprising:a memory; and a controller configured to cause:obtaining a first data stored in a first memory location of the memory; generating read values, based on a plurality of reads performed on the first data; computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and when one or more second memory locations of the memory are physically located within a target value,selecting one or more LLRs from the plurality of LLRs; and decoding data stored in the one or more second memory locations using the selected one or more LLRs. 9. The data storage system of claim 8 , wherein the controller is configured to cause: obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations,wherein selecting the one or more LLRs comprises selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics. 10. The data storage system of claim 8 , wherein the read values are correlated with the first data. 11. The data storage system of claim 8 , wherein the controller is configured to cause: placing the plurality of LLRs into a data structure associated with the first memory location. 12. The data storage system of claim 11 , wherein the controller is configured to cause: periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations. 13. The data storage system of claim 8 , wherein the controller is configured to cause:determining whether data in a third memory location is successfully decoded using a first read voltage; and when the third memory location is not successfully decoded using the first read voltage:decoding data in a fourth memory location using the first read voltage; and when the data in the fourth memory location is successfully decoded using the first read voltage:identifying the data in the fourth memory location as the first data. 14. The data storage system of claim 13 , wherein the controller is configured to cause: when the third memory location is successfully decoded using the first read voltage, identifying the data in the third memory location as the first data. 15. An apparatus, comprising:means for obtaining a first data stored in a first memory location of a memory; means for generating read values, based on a plurality of reads performed on the first data; means for computing a plurality of log likelihood ratios (LLRs), based on the read values and the first data; and when one or more second memory locations of the memory are physically located within a target value,means for selecting one or more LLRs from the plurality of LLRs; and means for decoding data stored in the one or more second memory locations using the selected one or more LLRs. 16. The apparatus of claim 15 , comprising: means for obtaining one or more first data retention characteristics of the first memory location and one or more second data retention characteristics of the one or more second memory locations,wherein means for selecting the one or more LLRs comprises means for selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics. 17. The apparatus of claim 15 , wherein the read values are correlated with the first data. 18. The apparatus of claim 15 , comprising: means for placing the plurality of LLRs into a data structure associated with the first memory location. 19. The apparatus of claim 18 , comprising: means for periodically updating one or more LLRs of the plurality of LLRs in the data structure, based on one or more decode operations performed on the data stored in the one or more second memory locations. 20. The apparatus of claim 15 , comprising:when data in a third memory location is not successfully decoded using a first read voltage:means for decoding data in a fourth memory location using the first read voltage; and when the data in the fourth memory location is successfully decoded using the first read voltage, means for treating the data in the fourth memory location as the first data; and when the data in the third memory location is successfully decoded using the first read voltage, means for treating the data in the third memory location as the first data.
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