FIG. 5A is a flow diagram illustrating an embodiment of a process 500A of generating soft-decision LLR inputs using multiple reads. The process 500A is described with reference to FIG. 1B for illustrative purposes, and may be performed by the error management module 140B of FIG. 1B. In one embodiment, the process begins at block 502 where correct reference data is determined. Then in block 504, multiple reads with different voltage thresholds are performed on the reference data. In block 506, LLR values are calculated based on comparison of multiple read values to correct reference data. In block 508, the LLR values are applied to decode target memory location(s). During decoding of a memory location, read errors may be encountered and soft-decision data may be used for decoding data stored in the memory location. Therefore, in certain embodiments, part of the process 500A (e.g., block 508) is performed after hard-decision error correction fails with respect to one or more target memory locations. Other parts of the process 500A may be performed periodically, apart from the occurrence of a failure to hard-decision error correction.