In one embodiment, these LLR values may be scaled by some constants. These calculated possible LLR values may be used to populate one or more LUTs, as described above. Furthermore, the system may be configured to dynamically update LUT entries based on ongoing calibration/decoding operations. In certain MLC embodiments, memory cells comprise upper and lower pages of data, wherein separate LUTs are generated for upper and lower page values. When reading upper page values, the controller 130 (FIG. 1A) may reference lower page data in order to distinguish between read levels R1 and R3, as illustrated in FIG. 2.
Multi-Read Approach—Apply LLR Values to Target Memory Location(s)
With further reference to FIG. 5A, at block 508 of the process 500A, the recorded possible LLR values are applied to decode additional target memory locations that are determined to have retention characteristics similar enough to those of the reference memory location that similar bit pattern probability characteristics can be assumed. For example, when the error management module 140B is unable to decode a memory location/page using hard-decision input, the error management module 140B identifies the LUT(s) associated with such location, looks up the bit patterns that occur based on multiple reads of the memory location, and provides a sequence of LLR values associated with the bit patterns in the LUT(s). In some embodiments, at least a portion of the possible LLR values generated from block 506 is selected at block 508 and applied to the decoding of the target memory location. For example, given this lookup table (LUT) of possible LLR values:
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