E0
0
0
1
0
0
. . .
E1
0
0
1
1
1
E2
1
0
1
1
0
LLR
V1
V0
V3
V2
V2
value
Similarly in FIG. 5B, at block 520 a sequence of LLRs based at least in part on the possible LLRs (from block 518) and on bit patterns from a multiple read operation on the target memory location is generated and data from a target memory location is decoded using the generated sequence of LLRs.
Other Variations