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Storage systems implementing offset erasure code stripes

專利號
US11175986B1
公開日期
2021-11-16
申請人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
John Stewart Best; Steven Robert Hetzler
IPC分類
G06F11/00; G06F11/10; G11B5/82; G11B7/24097; H03M13/15
技術(shù)領(lǐng)域
erasure,storage,strips,disk,optical,in,code,failure,stripe,disks
地域: NY NY Armonk

摘要

A computer-implemented method, according to one embodiment, includes: selecting strips from each storage unit for a given erasure code stripe such that the given erasure code stripe includes at most one strip from a high failure rate region of the respective storage unit, where each of the storage units include high and low failure rate regions. The selected strips are organized such that a number of each strip in the given erasure code stripe is offset from the remaining strips by an amount that is greater than a total number of strips in the high failure rate regions. The organized selected strips are further mapped to form the given erasure code stripe such that the high failure rate regions on each storage unit are mapped to one or more sequentially numbered strips, and the low failure rate regions are mapped to additional sequentially numbered strips.

說明書

Moreover, a system according to various embodiments may include a processor and logic integrated with and/or executable by the processor, the logic being configured to perform one or more of the process steps recited herein. The processor may be of any configuration as described herein, such as a discrete processor or a processing circuit that includes many components such as processing hardware, memory, I/O interfaces, etc. By integrated with, what is meant is that the processor has logic embedded therewith as hardware logic, such as an application specific integrated circuit (ASIC), a FPGA, etc. By executable by the processor, what is meant is that the logic is hardware logic; software logic such as firmware, part of an operating system, part of an application program; etc., or some combination of hardware and software logic that is accessible by the processor and configured to cause the processor to perform some functionality upon execution by the processor. Software logic may be stored on local and/or remote memory of any memory type, as known in the art. Any processor known in the art may be used, such as a software processor module and/or a hardware processor such as an ASIC, a FPGA, a central processing unit (CPU), an integrated circuit (IC), a graphics processing unit (GPU), etc.

It will be clear that the various features of the foregoing systems and/or methodologies may be combined in any way, creating a plurality of combinations from the descriptions presented above.

It will be further appreciated that embodiments of the present invention may be provided in the form of a service deployed on behalf of a customer to offer service on demand.

權(quán)利要求

1
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