Endurance enhancement scheme using memory re-evaluation
地域：
NY
NY Armonk
摘要
An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.
說明書
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The present invention relates to non-volatile memory, such as NAND Flash memory, and more specifically, this invention relates to re-evaluating units of non-volatile memory indicated for retirement.
Using Flash memory as an example, the performance characteristics of conventional NAND Flash-based solid state drives (SSDs) are fundamentally different from those of traditional hard disk drives (HDDs). Data in conventional SSDs is typically organized in physical pages of 4, 8, or 16 KB sizes. Moreover, page read operations in SSDs are typically one order of magnitude faster than write operations and latency neither depends on the current nor the previous location of operations.
However, in Flash-based SSDs, memory locations are erased in blocks prior to being written to. The size of an erase block is typically 128, 256 or 512 pages and the erase operations takes approximately one order of magnitude more time than a page program operation. Due to the intrinsic properties of NAND Flash, Flash-based SSDs write data out-of-place whereby a mapping table maps logical addresses of the written data to physical ones at a granularity of a logical page size of typically 4 KB. This mapping table is commonly referred to as the Logical-to-Physical Table (LPT). To improve storage efficiency, one or more logical pages can be mapped to a single physical memory page and/or logical pages might be split over more than one physical memory page. It follows that the LPT may additionally be responsible for keeping track of the necessary start, length and offset values for all logical page mappings.
權(quán)利要求
What is claimed is:1. An apparatus, comprising:non-volatile memory configured to store data; and a controller and logic integrated with and/or executable by the controller, the logic being configured to:determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition; re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block; indicate, by the controller, that the at least one block and/or the portion of a block remains usable in response to a result of the re-evaluation being to not retire the block; and indicate, by the controller, that the at least one block and/or the portion of a block is retired in response to the result of the re-evaluation being to retire the block, wherein the re-evaluating includes:assigning the at least one block and/or the portion of a block into a delay queue for at least a dwell time and/or a read delay, and in response to assigning the at least one block and/or the portion of a block into the delay queue for at least the dwell time and/or the read delay, calibrating the at least one block and/or the portion of a block by determining an optimal threshold voltage shift value for each of the at least one block and/or the portion of a block. 2. The apparatus as recited in claim 1 , wherein the re-evaluating includes performing one or more erase operations on the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to any of the one or more erase operations failing. 3. The apparatus as recited in claim 1 , wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to a number of calibration errors exceeding a retirement error count limit. 4. The apparatus as recited in claim 1 , wherein the re-evaluating includes performing a read sweep on the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to a number of read errors exceeding a retirement error count limit. 5. The apparatus as recited in claim 1 , wherein the re-evaluating includes:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to one or more write error occurring; and performing a read sweep on the at least one block and/or the portion of a block. 6. The apparatus as recited in claim 1 , wherein the non-volatile memory includes NAND Flash memory, wherein the re-evaluating is performed in response to determining that the at least one block of the non-volatile memory and/or portion of the block of the non-volatile memory meets the retirement condition. 7. The apparatus as recited in claim 1 , wherein the re-evaluating includes an operation selected from the group consisting of:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block; and performing a read sweep on the at least one block and/or the portion of a block. 8. A computer-implemented method, comprising:determining, by a computer, that at least one block of a non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition; re-evaluating, by the computer, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block; indicating, by the computer, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block; and indicating, by the computer, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block, wherein the re-evaluating includes:assigning the at least one block and/or the portion of a block into a delay queue for at least a dwell time and/or a read delay, and in response to assigning the at least one block and/or the portion of a block into the delay queue for at least the dwell time and/or the read delay, performing a calibration of the at least one block and/or the portion of a block by determining an optimal threshold voltage shift value for each of the at least one block and/or the portion of a block. 9. The method as recited in claim 8 , wherein the re-evaluating includes performing one or more erase operations on the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to any of the one or more erase operations failing. 10. The method as recited in claim 8 , wherein the re-evaluating includes writing data to the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to one or more write error occurring. 11. The method as recited in claim 8 , wherein the re-evaluating includes performing a read sweep on the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block in response to a number of read errors exceeding a retirement error count limit. 12. The method as recited in claim 8 , wherein the re-evaluating includes:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block; and performing a read sweep on the at least one block and/or the portion of a block, wherein the result of the re-evaluation is to retire the at least one block and/or the portion of a block when a number of calibration errors exceeds a retirement error count limit. 13. The method as recited in claim 8 , wherein the non-volatile memory includes NAND Flash memory, wherein the re-evaluating is performed in response to determining that the at least one block of the non-volatile memory and/or portion of the block of the non-volatile memory meets the retirement condition. 14. The computer-implemented method as recited in claim 8 , wherein the re-evaluating includes an operation selected from the group consisting of:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block; and performing a read sweep on the at least one block and/or the portion of a block. 15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to:determine, by the controller, that at least one block of a non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition; re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, wherein the re-evaluating includes:assigning the at least one block and/or the portion of a block into a delay queue for at least a dwell time and/or a read delay, and in response to assigning the at least one block and/or the portion of a block into the delay queue for at least the dwell time and/or the read delay, calibrating the at least one block and/or the portion of a block by determining an optimal threshold voltage shift value for each of the at least one block and/or the portion of a block; indicate, by the controller, that the at least one block and/or the portion of a block remains usable in response to a result of the re-evaluation being to not retire the block; and indicate, by the controller, that the at least one block and/or the portion of a block is retired in response to the result of the re-evaluation being to retire the block. 16. The computer program product as recited in claim 15 , wherein the re-evaluating includes at least one of:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block; and performing a read sweep on the at least one block and/or the portion of a block. 17. The computer program product as recited in claim 15 , wherein the re-evaluating includes:performing one or more erase operations on the at least one block and/or the portion of a block; writing data to the at least one block and/or the portion of a block; and performing a read sweep on the at least one block and/or the portion of a block. 18. The computer program product as recited in claim 15 , wherein the non-volatile memory includes NAND Flash memory, wherein the re-evaluating is performed in response to determining that the at least one block of the non-volatile memory and/or portion of the block of the non-volatile memory meets the retirement condition.
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