As Flash-based memory cells exhibit read errors and/or failures due to wear or other reasons, additional redundancy may be used within memory pages as well as across memory chips (e.g., RAID-5 and RAID-6 like schemes). The additional redundancy within memory pages may include error correction codes (ECC) which, for example, may include BCH codes. While the addition of ECC in pages is relatively straightforward, the organization of memory blocks into RAID-like stripes is more complex. For instance, individual blocks which exhibit errors are irreversibly retired over time. As the organization of stripes together with the LPT defines the placement of data, SSDs typically utilize a Log-Structured Array (LSA) architecture, which combines these two methods. However, the retirement of memory blocks requires either reorganization of the stripes, or capacity reduction of the stripe which is typically performed by conventional products. Moreover, when memory blocks are retired, write amplification increases, lifetime of the corresponding device decrease, etc.

The LSA architecture relies on out-of-place writes. In this approach, a memory page overwrite will result in writing the logical page data to a new location in memory, marking the old copy of the logical page data as invalid, and then updating the mapping information. Due to the limitations of current NAND memory technology, an invalidated data location cannot be reused until the entire block it belongs to has been erased. Before erasing, though, the block undergoes garbage collection, whereby any valid data in the block is relocated to a new block. Garbage collection of a block is typically deferred for as long as possible to maximize the amount of invalidated data in block, and thus reduce the number of valid pages that have to be relocated, as relocating data causes additional write operations, and thereby increases write amplification.