Cache and method for managing cache
地域：
Hsinchu
摘要
A cache and a method for managing a cache are provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit and is configured to find a storage space in the storage circuit and write the data to the storage space.
說明書
The present disclosure generally relates to caches, and, more particularly, to multi-level caches.
權(quán)利要求
What is claimed is:1. A cache, comprising:a storage circuit; a buffer circuit configured to store a target data in a first-in first-out manner; and a control circuit coupled to the storage circuit and the buffer circuit and configured to find a storage space in the storage circuit, to read the target data from the buffer circuit, and to write the target data to the storage space in the storage circuit; wherein the target data stored in the buffer circuit is same as the target data written to the storage space in the storage circuit. 2. The cache of claim 1 , wherein the target data is a first target data, and when a second target data is being written to the cache, the control circuit writes the second target data to the buffer circuit without checking the storage circuit. 3. The cache of claim 1 , wherein the target data is a first target data, and when the control circuit checks whether the cache contains a second target data, the control circuit checks whether the storage circuit and the buffer circuit store the second target data. 4. The cache of claim 1 , wherein a capacity of the buffer circuit is smaller than a capacity of the storage circuit. 5. The cache of claim 1 , wherein the buffer circuit is implemented by registers. 6. The cache of claim 1 , wherein the buffer circuit is implemented by static random-access memories (SRAMs). 7. The cache of claim 1 , wherein when the cache is in an idle state, and the buffer circuit is not empty, the control circuit finds the storage space in the storage circuit and writes the target data to the storage space. 8. A method for managing a cache, the cache comprising a storage circuit and a buffer circuit, the buffer circuit storing data in a first-in first-out manner, the method comprising:when a target data is being written to the cache, writing the target data to the buffer circuit without checking the storage circuit; and finding a storage space in the storage circuit and writing the target data read from the buffer circuit to the storage space in the storage circuit; wherein the target data written to the buffer circuit is same as the target data written to the storage space in the storage circuit. 9. The method of claim 8 further comprising:checking whether the storage circuit and the buffer circuit store the target data when checking whether the cache contains the target data. 10. The method of claim 8 , wherein a capacity of the buffer circuit is smaller than a capacity of the storage circuit. 11. The method of claim 8 , wherein the buffer circuit is implemented by registers. 12. The method of claim 8 , wherein the buffer circuit is implemented by static random-access memories (SRAMs). 13. The method of claim 8 , wherein when the cache is in an idle state, and the buffer circuit is not empty, the step of finding the storage space in the storage circuit and writing the target data to the storage space is performed. 14. A cache comprising:a register storing a register value; a first level cache, coupled to the register and comprising a first control circuit that controls, according to the register value, the first level cache to operate in an inclusive mode or an exclusive mode; and a second level cache, coupled to the register and comprising a second control circuit that controls, according to the register value, the second level cache to operate in the inclusive mode or the exclusive mode; wherein when the register value is a first value, both the first level cache and the second level cache operate in the inclusive mode, and when the register value is a second value different from the first value, both the first level cache and the second level cache operate in the exclusive mode. 15. The cache of claim 14 , wherein the second level cache is shared by a first core and a second core of a processor, the first core executes a first program and the second core executes a second program, and when the first program and the second program are programs sharing instructions or data, the register value corresponds to the inclusive mode. 16. The cache of claim 14 , wherein the second level cache is shared by a first core and a second core of a processor, the first core executes a first program and the second core executes a second program, and when the first program and the second program are programs not sharing instructions or data, the register value corresponds to the exclusive mode. 17. The cache of claim 14 , wherein the second level cache comprises:a storage circuit; a buffer circuit configured to store a data in a first-in first-out manner; and a control circuit coupled to the storage circuit and the buffer circuit and configured to find a storage space in the storage circuit and to write the data to the storage space. 18. The cache of claim 17 , wherein when a target data is being written to the second level cache, the control circuit writes the target data to the buffer circuit without checking the storage circuit. 19. The cache of claim 17 , wherein when the control circuit checks whether the second level cache contains a target data, the control circuit checks whether the storage circuit and the buffer circuit store the target data. 20. The cache of claim 17 , wherein a capacity of the buffer circuit is smaller than a capacity of the storage circuit.
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