As can be seen from the flow of FIG. 5, the buffer circuit 434 may store multiple target data at the same time, and the control circuit 432 sequentially reads the target data from the buffer circuit 434 in a FIFO manner and writes the target data to the storage circuit 436. In some embodiments, step S570 can be simplified when the data in the buffer circuit 434 has the same format as the data in the storage circuit 436 (e.g., in the format of a line data).

Theoretically, only one cycle of the system clock is needed to complete step S510 because the control circuit 432 is not required to check the tags in the storage circuit 436 to find a suitable storage space (either an empty storage space or a space occupied by a data to be evicted) in step S510. In comparison, the control circuit 432 needs at least two cycles of the system clock (depending on the size of the storage circuit 436) to directly write the target data to the storage circuit 436 because the control circuit 432 needs to check the tags when writing the target data to the storage circuit 436. In other words, the buffer circuit 434 can increase the speed of the L2 cache 430.