The idle state of step S520 includes two scenarios: (1) the period in which the control circuit 432 has no read/write operations to be processed; and (2) when a read miss occurs in the L2 cache 430, the period from the control circuit 432 requesting data from the system memory 440 to the control circuit 432 receiving the response from the system memory 440. Because the number of cycles of the system clock required for one access to the system memory 440 is typically much greater than the number of cycles of the system clock required for the control circuit 432 to write data to storage circuit 436, the control circuit 432 has sufficient time in scenario (2) to perform steps S560 and S570.

In summary, for the processor 410, the operation of the L2 cache 430 takes only one cycle of the system clock whether when a read miss occurs in the inclusive mode or when a read hit occurs in the exclusive mode. Therefore, the processor 410 is not stalled, which greatly improves the performance of the electronic device 400.