FIG. 6 illustrates a flow chart of step S540 in FIG. 5 according to an embodiment of the present disclosure. When the L1 cache 420 requests the L2 cache 430 for data after a read miss occurs in the L1 cache 420, the control circuit 432 checks whether the buffer circuit 434 and the storage circuit 436 store the target data (step S610). When a read hit occurs in the L2 cache (i.e., the buffer circuit 434 or the storage circuit 436 stores the target data, step S620 being positive), the control circuit 432 reads the target data and sends the target data to the L1 cache 420 (step S630). When a read miss occurs in the L2 cache (i.e., neither the buffer circuit 434 nor the storage circuit 436 stores the target data, step S620 being negative), the control circuit 432 requests the system memory 440 for data (step S640).