FIG. 7 is a block diagram of an electronic device according to another embodiment of the present disclosure. The electronic device 70 includes a processor 72, an L2 cache 74 and a register 76. The processor 72 includes a core 720 and a core 730. The core 720 includes a processing unit 722 and an L1 cache 724. The L1 cache 724 includes a control circuit 7241 and a storage circuit 7242. The core 730 includes a processing unit 732 and an L1 cache 734. The L1 cache 734 includes a control circuit 7341 and a storage circuit 7342. In short, the processor 72 is a multi-core architecture. The core 720 and the core 730 each has its own L1 cache (724 and 734, respectively) and share the L2 cache 74. The L2 cache 74 includes a control circuit 742, a buffer circuit 744 and a storage circuit 746. The functions of the control circuit 742, the buffer circuit 744 and the storage circuit 746 are similar to the control circuit 432, the buffer circuit 434 and the storage circuit 436, respectively, and are thus omitted for brevity. The control circuit 7241, the control circuit 7341 and the control circuit 742 are coupled to the register 76 and configured to read the register value of the register 76.