The control circuit 7241 of the L1 cache 724, the control circuit 7341 of the L1 cache 734, and the control circuit 742 of the L2 cache 74 refer to the register value of the register 76 to respectively control the L1 cache 724, the L1 cache 734 and the L2 cache 74 to operate in the inclusive mode or the exclusive mode. In other words, the L1 cache and the L2 cache are controlled in a programmable manner to operate in either the inclusive mode or the exclusive mode. In this way, there is no need to decide the operation mode of the L1 cache 724, the L1 cache 734 and the L2 cache 74 when the electronic device 70 is being designed. Instead, the user can set the register value of the register 76 after the completion of the circuit based on the practical applications. That is, dynamic adjustments are feasible. In some embodiments, the register 76 can be a control register of the processor 72.

The followings are some application examples of the electronic device 70.

Examples (1): in a case where the core 720 and the core 730 operate in a parallel processing mode (i.e., both executing the same program), the register value of the register 76 can be set to a first value (e.g., 1) such that the L1 cache 724, the L1 cache 734 and the L2 cache 74 operate in the inclusive mode.

Example (2): in a case where the core 720 and the core 730 respectively execute the first program and the second program that share instructions and/or data, the register value of the register 76 can be set to a first value (e.g., 1) such that the L1 cache 724, the L1 cache 734 and the L2 cache 74 operate in the inclusive mode.