Example (3): in a case where the core 720 and the core 730 respectively execute the first program and the second program that do not share instructions and/or data (i.e., the first program is independent of the second program), the register value of the register 76 can be set to a second value (e.g., 0) such that the L1 cache 724, the L1 cache 734 and the L2 cache 74 operate in the exclusive mode.

In examples (1) and (2), the inclusive mode can reduce the number of times of moving data (i.e., improving the hit rate), and so the performance of the electronic device 70 can be improved. In example (3), the L1 cache 724, the L1 cache 734 and the L2 cache 74 store more instructions and/or data in the exclusive mode, and so the performance of the electronic device 70 can be improved.

In some embodiments, the control circuit 432, the control circuit 7241, the control circuit 7341 and the control circuit 742 can be implemented by a finite state machine, which includes multiple logic circuits.

Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method embodiment through the disclosure of the device embodiment, repeated and redundant description is thus omitted. Please note that there is no step sequence limitation for the method embodiments as long as the execution of each step is applicable. Furthermore, the shape, size, and ratio of any element and the step sequence of any flow chart in the disclosed figures are exemplary for understanding, not for limiting the scope of this disclosure.