FIG. 2 is a partial flow chart of the electronic device 100 operating in the inclusive mode. When a read miss occurs in the L1 cache 120, the L1 cache 120 requests the L2 cache 130 for data (step S210). In step S220, the control circuit 132 checks whether the data requested by the L1 cache 120 is stored in the storage circuit 136. If the data requested by the L1 cache 120 is not stored in the storage circuit 136 (i.e., a read miss in L2 cache), the control circuit 132 requests the system memory 140 for data (step S230). Next, the L2 cache 130 receives data from the system memory 140 (step S240) and then sends the data to the L1 cache 120 (step S250). After receiving the data from the L2 cache 130, the L1 cache 120 stores the data. Finally, the L1 cache 120 broadcasts the data to the L2 cache 130 (step S260). In step S260, the control circuit 132 must check the tags in the storage circuit 136 and write the data to the storage circuit 136. Since the capacity of the L2 cache 130 is typically greater than the capacity of the L1 cache 120, accessing the storage circuit 136 consumes more time. For example, if accessing the L1 cache 120 requires one cycle of the system clock, it may take two to three cycles to access the storage circuit 136. Since step S260 is relatively time consuming, the control circuit 132 cannot immediately proceed to carry out the next access command, leading to stalls in the processor 110.