FIG. 3 is a partial flow chart of the electronic device 100 operating in the exclusive mode. When a read miss occurs in the L1 cache 120, the L1 cache 120 requests the L2 cache 130 for data (step S310). In step S320, the control circuit 132 checks whether the data requested by the L1 cache 120 is stored in the storage circuit 136. If the data requested by the L1 cache 120 is stored in the storage circuit 136 (i.e., a read hit in the L2 cache), the control circuit 132 sends the data to the L1 cache 120 (step S330). Next, a line data is evicted from the L1 cache 120 and then written to the L2 cache 130 (step S340). In step S340, the control circuit 132 must check the tags in the storage circuit 136 and write the line data to an appropriate location in the storage circuit 136. Since accessing the storage circuit 136 is relatively time consuming, step S340 may prevent the control circuit 132 from immediately proceeding to carry out the next access command, leading to stalls in the processor 110.
SUMMARY
In view of the issues of the prior art, an object of the present disclosure is to provide a cache and a method for managing a cache, so as to improve the performance of the electronic device.
A cache is provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit is configured to store a data in a first-in first-out manner. The control circuit is coupled to the storage circuit and the buffer circuit and configured to find a storage space in the storage circuit and to write the data to the storage space.
