A method for managing a cache is also provided. The cache includes a storage circuit and a buffer circuit. The buffer circuit stores data in a first-in first-out manner. The method includes the following steps: when a target data is being written to the cache, writing the target data to the buffer circuit without checking the storage circuit; and finding a storage space in the storage circuit and writing the target data to the storage space.

A cache is also provided. The cache includes a first level cache, a second level cache and a register. The first level cache includes a first control circuit. The second level cache includes a second control circuit. The register is coupled to the first control circuit and the second control circuit. The first control circuit and the second control circuit refer to a register value of the register to respectively control the first level cache and the second level cache to operate in an inclusive mode or an exclusive mode.

According to the present disclosure, the access speed of the cache is improved due to the arrangement of a buffer circuit in the cache. Compared with the conventional technology, processor stall is less likely to occur in the electronic device employing the cache of the present disclosure. Furthermore, the cache of the present disclosure is easy to switch between the inclusive mode and the exclusive mode.

These and other objectives of the present disclosure no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings.