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Cache and method for managing cache

專利號
US11176039B2
公開日期
2021-11-16
申請人
REALTEK SEMICONDUCTOR CORPORATION(TW Hsinchu)
發(fā)明人
Jui-Yuan Lin; Yen-Ju Lu
IPC分類
G06F12/00; G06F12/0811
技術(shù)領(lǐng)域
cache,circuit,l1,l2,storage,data,in,buffer,control,step
地域: Hsinchu

摘要

A cache and a method for managing a cache are provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit and is configured to find a storage space in the storage circuit and write the data to the storage space.

說明書

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The disclosure herein includes caches and a method for managing caches. On account of that some or all elements of the cache could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure, and that this omission nowhere dissatisfies the specification and enablement requirements. Some or all of the processes of the method for managing caches may be implemented by software and/or firmware and can be performed by the cache or its equivalent. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present disclosure, which means that the scope of the present disclosure is not limited to the embodiments in the specification.

權(quán)利要求

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