FIG. 4 illustrates a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 400 includes a processor 410, an L1 cache 420, an L2 cache 430 and a system memory 440. The L2 cache 430 includes a control circuit 432, a buffer circuit 434 and a storage circuit 436. The buffer circuit 434 stores data in a first-in first-out (FIFO) manner, while the storage circuit 436 does not store data in a FIFO manner. In some embodiments, the capacity of the buffer circuit 434 is smaller than the capacity of the storage circuit 436. Thus, the time the control circuit 432 takes to access the buffer circuit 434 may be less than the time the control circuit 432 takes to access the storage circuit 436. That is to say, the control circuit 432 may have a higher speed to access the buffer circuit 434 than to access the storage circuit 436. The storage circuit 436 stores multiple tags and multiple data corresponding to the tags. The data structure of the storage circuit 436 is well known to people having ordinary skill in the art and is thus omitted for brevity. The buffer circuit 434 can be implemented by SRAMs or registers, e.g., flip-flops, and the storage circuit 436 can be implemented by SRAMs. The L1 cache 420 and the L2 cache 430 can operate in the inclusive mode or the exclusive mode.