FIG. 5 illustrates a flow chart of a cache management method according to an embodiment of the present disclosure. The flow of FIG. 5 applies to both the inclusive mode and the exclusive mode. When the control circuit 432 receives the target data from the L1 cache 420 or the system memory 440, and when the control circuit 432 is about to store the target data, the control circuit 432 writes the target data to the buffer circuit 434 without checking the tags in the storage circuit 436 (step S510). Next, the control circuit 432 determines whether the L2 cache 430 is in an idle state (step S520). If step S520 is negative (NO branch), the control circuit 432 further determines whether another target data needs to be written to the L2 cache 430 (step S530). If step S530 is positive (YES branch), the control circuit 432 writes said another target data to the buffer circuit 434 (step S510). If step S530 is negative (NO branch), the control circuit 432 searches for data and/or send the data (step S540), and this step includes accessing the buffer circuit 434 and/or the storage circuit 436. After step S540 is completed, the flow returns to step S520.