白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Integration of application indicated minimum time to cache for a two-tiered cache management mechanism

專(zhuān)利號(hào)
US11176057B2
公開(kāi)日期
2021-11-16
申請(qǐng)人
INTERNATIONAL BUSINESS MACHINES CORPORATION（US NY Armonk）
發(fā)明人
Lokesh Mohan Gupta; Matthew G. Borlick; Beth Ann Peterson; Kyler A. Anderson
IPC分類(lèi)
G06F12/123; G06F12/0891; G06F12/0893
技術(shù)領(lǐng)域
cache,scm,retention,minimum,dram,tracks,track,lru,in,time
地域： NY NY Armonk

摘要

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

說(shuō)明書(shū)

BACKGROUND 1. Field

Embodiments relate to the integration of application indicated minimum time to cache for a two-tiered cache management mechanism.

2. Background

In certain storage system environments, a storage controller (or a storage controller complex) may comprise a plurality of storage servers that are coupled to each other. The storage controller allows host computing systems to perform input/output (I/O) operations with storage devices controlled by the storage controller, where the host computing systems may be referred to as hosts.

The storage controller may include two or more servers, where each server may be referred to as a node, a storage server, a processor complex, a Central Processor Complex (CPC), or a Central Electronics Complex (CEC). Each server may have a plurality of processor cores and the servers may share the workload of the storage controller. In a two server configuration of the storage controller that is also referred to as a dual-server based storage controller, in the event of a failure of one of the two servers, the other server that has not failed may take over the operations performed by the failed server.

權(quán)利要求

1
What is claimed is:1. A method, comprising:receiving from a host application, an indication of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks;based on the first minimum retention time, setting a second minimum retention time for the first plurality of tracks for the first type of memory and a third minimum retention time for the first plurality of tracks for the second type of memory; anddemoting a track of the first plurality of tracks from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.2. The method of claim 1, wherein the first type of memory is a dynamic random access memory (DRAM) cache and the second type of memory is a storage class memory (SCM) cache, and wherein the second minimum retention time is a DRAM cache minimum retention time and the third minimum retention time is a SCM cache minimum retention time.3. The method of claim 2, the method further comprising:demoting, by a cache management application, a track of the first plurality of tracks from the SCM cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the SCM cache and the track has been in the SCM cache for a time that exceeds the SCM cache minimum retention time.4. The method of claim 2, wherein the indication of the first minimum retention time in cache comprises an individual minimum retention time for the DRAM cache and an individual minimum retention time for the SCM cache, wherein the DRAM cache minimum retention time is set to the individual minimum retention time for the DRAM cache, and wherein the SCM cache minimum retention time is set to the individual minimum retention time for the SCM cache.5. The method of claim 2, wherein the indication of the first minimum retention time in cache comprises an aggregate minimum retention time for the DRAM cache and the SCM cache, wherein the DRAM cache minimum retention time is set to a predetermined percentage of the aggregate minimum retention time, and wherein the SCM cache minimum retention time is set to a remaining percentage of the aggregate minimum retention time.6. The method of claim 2, wherein while promoting a track securing more than a predetermined number of hits from the SCM cache to the DRAM cache, unless a new first minimum retention time is provided for the track by the host application, a cache management application sets the DRAM cache minimum retention time to a difference of the SCM cache minimum retention time and the time the track has spent in the SCM cache prior to being promoted to the DRAM cache.7. The method of claim 2, wherein promoting a track from the DRAM cache to SCM cache comprises adding an unutilized time for the track in the DRAM cache to the SCM cache minimum retention time, wherein the DRAM cache has a lower latency and a lower storage capacity than the SCM cache, and wherein the DRAM cache and the SCM cache form a two-tier cache with the DRAM cache being a higher tier and the SCM cache being a lower tier, and wherein for the second plurality of tracks a cache management application does not set the DRAM cache minimum retention time and the SCM cache minimum retention time.8. A system, comprising:a memory; anda processor coupled to the memory, wherein the processor performs operations, the operations performed by the processor comprising:receiving from a host application, an indication of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks;based on the first minimum retention time, setting a second minimum retention time for the first plurality of tracks for the first type of memory and a third minimum retention time for the first plurality of tracks for the second type of memory; anddemoting a track of the first plurality of tracks from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.9. The system of claim 8, wherein the first type of memory is a dynamic random access memory (DRAM) cache and the second type of memory is a storage class memory (SCM) cache, and wherein the second minimum retention time is a DRAM cache minimum retention time and the third minimum retention time is a SCM cache minimum retention time.10. The system of claim 9, the operations further comprising:demoting, by a cache management application, a track of the first plurality of tracks from the SCM cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the SCM cache and the track has been in the SCM cache for a time that exceeds the SCM cache minimum retention time.11. The system of claim 9, wherein the indication of the first minimum retention time in cache comprises an individual minimum retention time for the DRAM cache and an individual minimum retention time for the SCM cache, wherein the DRAM cache minimum retention time is set to the individual minimum retention time for the DRAM cache, and wherein the SCM cache minimum retention time is set to the individual minimum retention time for the SCM cache.12. The system of claim 9, wherein the indication of the first minimum retention time in cache comprises an aggregate minimum retention time for the DRAM cache and the SCM cache, wherein the DRAM cache minimum retention time is set to a predetermined percentage of the aggregate minimum retention time, and wherein the SCM cache minimum retention time is set to a remaining percentage of the aggregate minimum retention time.13. The system of claim 9, wherein while promoting a track securing more than a predetermined number of hits from the SCM cache to the DRAM cache, unless a new first minimum retention time is provided for the track by the host application, a cache management application sets the DRAM cache minimum retention time to a difference of the SCM cache minimum retention time and the time the track has spent in the SCM cache prior to being promoted to the DRAM cache.14. The system of claim 9, wherein promoting a track from the DRAM cache to SCM cache comprises adding an unutilized time for the track in the DRAM cache to the SCM cache minimum retention time, wherein the DRAM cache has a lower latency and a lower storage capacity than the SCM cache, and wherein the DRAM cache and the SCM cache form a two-tier cache with the DRAM cache being a higher tier and the SCM cache being a lower tier, and wherein for the second plurality of tracks a cache management application does not set the DRAM cache minimum retention time and the SCM cache minimum retention time.15. A computer program product, the computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to perform operations, the operations comprising:receiving from a host application, an indication of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks;based on the first minimum retention time, setting a second minimum retention time for the first plurality of tracks for the first type of memory and a third minimum retention time for the first plurality of tracks for the second type of memory; anddemoting a track of the first plurality of tracks from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.16. The computer program product of claim 15, wherein the first type of memory is a dynamic random access memory (DRAM) cache and the second type of memory is a storage class memory (SCM) cache, and wherein the second minimum retention time is a DRAM cache minimum retention time and the third minimum retention time is a SCM cache minimum retention time.17. The computer program product of claim 16, the operations further comprising:demoting, by a cache management application, a track of the first plurality of tracks from the SCM cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the SCM cache and the track has been in the SCM cache for a time that exceeds the SCM cache minimum retention time.18. The computer program product of claim 16, wherein the indication of the first minimum retention time in cache comprises an individual minimum retention time for the DRAM cache and an individual minimum retention time for the SCM cache, wherein the DRAM cache minimum retention time is set to the individual minimum retention time for the DRAM cache, and wherein the SCM cache minimum retention time is set to the individual minimum retention time for the SCM cache.19. The computer program product of claim 16, wherein the indication of the first minimum retention time in cache comprises an aggregate minimum retention time for the DRAM cache and the SCM cache, wherein the DRAM cache minimum retention time is set to a predetermined percentage of the aggregate minimum retention time, and wherein the SCM cache minimum retention time is set to a remaining percentage of the aggregate minimum retention time.20. The computer program product of claim 16, wherein while promoting a track securing more than a predetermined number of hits from the SCM cache to the DRAM cache, unless a new first minimum retention time is provided for the track by the host application, a cache management application sets the DRAM cache minimum retention time to a difference of the SCM cache minimum retention time and the time the track has spent in the SCM cache prior to being promoted to the DRAM cache.
微信群二維碼
意見(jiàn)反饋