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Integration of application indicated minimum time to cache for a two-tiered cache management mechanism

專利號
US11176057B2
公開日期
2021-11-16
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Lokesh Mohan Gupta; Matthew G. Borlick; Beth Ann Peterson; Kyler A. Anderson
IPC分類
G06F12/123; G06F12/0891; G06F12/0893
技術領域
cache,scm,retention,minimum,dram,tracks,track,lru,in,time
地域: NY NY Armonk

摘要

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

說明書

In certain embodiments, an application specifies individual minimum retention times for the DRAM cache and the SCM cache, or just one overall minimum retention time for both the DRAM cache and the SCM cache. For example, in certain embodiments a database management application may indicate that indexes are to be kept in DRAM cache for 1 minute and in SCM cache for 2 minutes, or the database management application may just provide an overall minimum retention time indication to keep indexes for a minimum duration of 3 minutes in both the DRAM cache and SCM cache together (i.e., the indexes should be maintained for at least 3 minutes in aggregate in the DRAM cache and the SCM cache).

Certain embodiments provide mechanisms to keep tracks in DRAM cache for the minimum retention time indicated for the DRAM cache and in SCM cache for the minimum retention time indicated for the SCM cache, if both the DRAM minimum retention time and the SCM minimum retention time are indicated.

If only an overall minimum retention time is indicated for a track then certain embodiments retain tracks in the DRAM cache for 50% (or some other percentage) of overall minimum retention time in the DRAM cache. When demoting a track from the DRAM cache to SCM cache, the remaining minimum time for retention is computed, and the track is maintained in the SCM cache for the computed time. As a result, the DRAM cache which is smaller in size in comparison to the SCM cache is prevented from becoming fill while the overall minimum retention time indicated by an application is satisfied.

權利要求

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