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Integration of application indicated minimum time to cache for a two-tiered cache management mechanism

專利號
US11176057B2
公開日期
2021-11-16
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Lokesh Mohan Gupta; Matthew G. Borlick; Beth Ann Peterson; Kyler A. Anderson
IPC分類
G06F12/123; G06F12/0891; G06F12/0893
技術(shù)領(lǐng)域
cache,scm,retention,minimum,dram,tracks,track,lru,in,time
地域: NY NY Armonk

摘要

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

說明書

Certain embodiments provide improvements to computer technology, by integrating application indicated minimum retention time for tracks to LRU based track demoting schemes in a cache management system of a storage controller having a two-tier cache comprising a DRAM cache and a SCM cache. As a result, caching operations in a storage controller takes account of hints (i.e., indications) provided by an application to retain certain tracks in cache for at least a minimum amount of time. However, the cache is prevented from becoming full (i.e., tracks cannot be staged to the cache) when too many tracks have a minimum retention time. The cache is also prevented from becoming full when too high a percentage of tracks have a minimum retention time. A LRU list is augmented with the information on whether a track has a minimum retention time indicated by an application, and unless the cache is in danger of being full, such requests for minimum retention time is adhered to by the cache management application of the storage controller. As a result, the needs for minimum retention time for a subset of tracks is balanced with the demoting needs of the cache to prevent the cache from becoming full in a two-tier cache. Additionally, time for which a track is maintained in the DRAM cache and SCM cache may be adjusted during promotion of a track to the DRAM cache or to the SCM cache.

EXEMPLARY EMBODIMENTS

FIG. 1 illustrates a block diagram of a computing environment 100 comprising a storage controller 102 with a two-tier cache 104 coupled to one or more hosts 106 and one or more storage devices 108, 110, in accordance with certain embodiments.

權(quán)利要求

1
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