FIG. 8 illustrates a flowchart that shows the demote process for a track in the DRAM cache 112 as performed by a cache management application 116, in accordance with certain embodiments. The operations shown in FIG. 8 improve the performance of the storage controller 102 by reducing cache misses should there be indications of minimum retention time for certain tracks in the DRAM cache 112.

Control starts at block 802 in which the cache management application 116 starts evaluating the track at the LRU end of the LRU list 118 for potential demotion from the DRAM cache 112. Control proceeds to block 804 in which the cache management application 116 determines whether the track has a minimum retention time. If not (“No” branch 806), then the cache management application 116 demotes (at block 808) the track from the DRAM cache 112.

If at block 804 the cache management application 116 determines that the track has a minimum retention time (“Yes” branch 810) then control proceeds to block 812 in which the cache management application 116 determines whether the difference of the current time from the timestamp of the track is greater than the minimum retention time of the track (i.e., whether the track has been in the DRAM cache for a time that exceeds the minimum retention time). If so (“Yes” branch 814) then the track is demoted (at block 816) and the cache management application 116 decrements (i.e., subtracts the number 1) the number of minimum retention time tracks in the DRAM cache 112 (at block 818).