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Integration of application indicated minimum time to cache for a two-tiered cache management mechanism

專利號
US11176057B2
公開日期
2021-11-16
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION（US NY Armonk）
發(fā)明人
Lokesh Mohan Gupta; Matthew G. Borlick; Beth Ann Peterson; Kyler A. Anderson
IPC分類
G06F12/123; G06F12/0891; G06F12/0893
技術領域
cache,scm,retention,minimum,dram,tracks,track,lru,in,time
地域： NY NY Armonk

摘要

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

說明書

If track gets a hit in SCM cache and subsequently promoted to DRAM cache (at block 1202) then determination is made (at block 1204) as to whether new minimum retention times have been specified by the host application for the track for the DRAM cache. If so (“Yes” branch 1206), then the cache management application 116 updates (at block 1208) the minimum retention times for the track. If not (“No” branch 1210), then the cache management application 116 computes new remaining minimum time based on the calculation “SCM minimum time—Time stayed in SCM cache” (reference numeral 1212). This new minimum time is now stored as DRAM minimum retention time and SCM minimum retention time is set to 0. This is done because the track is getting good hits and should remain in faster cache (i.e., the DRAM cache) for the entirety of its remaining minimum retention time.

FIG. 13 illustrates a flowchart 1300 that shows operations for managing a two-tier cache as performed by the cache management application 116, in accordance with certain embodiments.

權利要求

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