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Integration of application indicated minimum time to cache for a two-tiered cache management mechanism

專利號
US11176057B2
公開日期
2021-11-16
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Lokesh Mohan Gupta; Matthew G. Borlick; Beth Ann Peterson; Kyler A. Anderson
IPC分類
G06F12/123; G06F12/0891; G06F12/0893
技術領域
cache,scm,retention,minimum,dram,tracks,track,lru,in,time
地域: NY NY Armonk

摘要

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

說明書

FIG. 16 illustrates a block diagram that shows certain elements that may be included in the storage controller 102 or the host 106, or other computational devices in accordance with certain embodiments. The system 1600 may include a circuitry 1602 that may in certain embodiments include at least a processor 1604. The system 1600 may also include a memory 1606 (e.g., a volatile memory device), and storage 1608. The storage 1608 may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage 1608 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 1600 may include a program logic 1610 including code 1612 that may be loaded into the memory 1606 and executed by the processor 1604 or circuitry 1602. In certain embodiments, the program logic 1610 including code 1612 may be stored in the storage 1608. In certain other embodiments, the program logic 1610 may be implemented in the circuitry 1602. One or more of the components in the system 1600 may communicate via a bus or via other coupling or connection 1614. Therefore, while FIG. 16 shows the program logic 1610 separately from the other elements, the program logic 1610 may be implemented in the memory 1606 and/or the circuitry 1602.

權利要求

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