FIG. 5 illustrates a block diagram that shows operations performed when aggregate minimum retention time for cache is provided by a host application, in accordance with certain embodiments;

FIG. 6 illustrates a flowchart that shows operations for track access, in accordance with certain embodiments;

FIG. 7 illustrates a block diagram that shows addition of a track with a minimum retention time to the cache, in accordance with certain embodiments;

FIG. 8 illustrates a flowchart that shows the demote process for a track in the DRAM cache as performed by a cache management application, in accordance with certain embodiments;

FIG. 9 illustrates a block diagram that shows condition for promotion to SCM cache on demotion from DRAM cache, in accordance with certain embodiments:

FIG. 10 illustrates a block diagram that shows predetermined conditions based on which a demotion decision for a track with minimum retention time is made, in accordance with certain embodiments:

FIG. 11 illustrates a flowchart that shows the demote process for a track in the SCM cache as performed by the cache management application, in accordance with certain embodiments:

FIG. 12 illustrates a flowchart that shows operations for promotion from SCM cache to DRAM cache, in accordance with certain embodiments:

FIG. 13 illustrates a flowchart that shows operations for managing a two-tier cache, in accordance with certain embodiments: