According to an embodiment, a path between the multiplexer 150 and the first input/output interface 140 may be referred to as a first data path, and a path between the multiplexer 150 and the second input/output interface 160 may be referred to as a second data path. The multiplexer 150 may perform path switching between the first data path and the second data path. The multiplexer 150 may perform a selective connection to the first input/output interface 140 or the second input/output interface 160 of the processor 110. The first data path may be referred to as a pogo path, and the second data path may be referred to as a USB path.

According to an embodiment, the multiplexer 150 may be arranged between the processor 110 (or the identification circuit 130) and the input/output interfaces 140 and 160 and may electrically connect one of the input/output interfaces 140 and 160 and the processor 110 (or the identification circuit 130). According to an embodiment, the multiplexer 150 may not provide a data communication connection between the second input/output interface 160 and the processor 110 while being connected to the first input/output interface 140.

According to an embodiment, the identification circuit 130 may control the data paths between the multiplexer 150 and the input/output interfaces 140 and 160. The identification circuit 130 may control the multiplexer 150 such that the processor 110 is connected to the first data path or the second data path.