According to aspects of the present invention, a capacitor based resistive processing unit can employ a first capacitor for storing a weight value. The weight value can be updated periodically for accuracy in response to an error signal by using a second capacitor to transfer charge towards or away from the first capacitor.

When using the second capacitor to perform a positive weight change to the weight stored in the first capacitor, charge is added to the capacitor through a positive update 404 to a voltage differential corresponding to the first capacitor. However, when decreasing the weight value stored in the first capacitor, charge is removed from the first capacitor through a negative update 402 to the voltage differential. By performing the update using the second capacitor, the positive update 404 and the negative update 402 are symmetrical with respect to the voltage of the first capacitor. As a result, as the voltage across the first capacitor increases, the change in the voltage in the positive or negative direction for an update are about equal in magnitude to achieve the desired weight update. As a result, the capacitor based resistive processing unit has more symmetrical weight updating due to the second capacitor. Accordingly, the resistive processing unit is more suitable to train neural networks while having smaller components for improved scalability.

Referring now to FIG. 8, a block/flow diagram of a system/method for symmetric weight updating with a capacitor based analog processing unit, in accordance with an embodiment of the present invention.

At block 801, a charge corresponding to a weight value is stored with a first capacitor.