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Capacitor based resistive processing unit with symmetric weight update

專利號(hào)
US11176451B2
公開(kāi)日期
2021-11-16
申請(qǐng)人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Yulong Li; Paul M. Solomon; Effendi Leobandung
IPC分類
G06N3/063; G06N3/08; G11C11/24; G11C11/54
技術(shù)領(lǐng)域
capacitor,charge,first,gates,second,voltage,weight,analog,pre,stochastic
地域: NY NY Armonk

摘要

Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.

說(shuō)明書(shū)

In accordance with another embodiment of the present invention, a method for symmetrical weight updating of capacitor based resistive processing unit is described. The method includes storing a charge corresponding to a weight value with a first capacitor. The charge stored in the first capacitor is read with a readout circuit to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. The weight value stored in the first capacitor is updated with an update circuit, including transferring an amount of charge from a second capacitor to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description will provide details of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a diagram showing an array of analog processing units, in accordance with an embodiment of the present invention;

FIG. 2 is a diagram showing a capacitor based analog processing unit, in accordance with an embodiment of the present invention;

權(quán)利要求

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