FIG. 8 is a schematic structural diagram of a game stage switching apparatus according to the embodiments of the present application. A game stage switching apparatus 310 includes a processor 311, and a memory 314. The game stage switching apparatus 310 may further include an input device 312 an output device 313, and a bus 315. The input device 312, the output device 313, the memory 314, and the processor 311 are interconnected by the bus 315.

The memory includes, but is not limited to, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), or a Compact Disc Read-Only Memory (CD-ROM), and is used for storing related instructions and data.

The input device may be used to input data and/or signals, and the output device may be used to output data and/or signals. The output device and the input device may be independent devices, or may be an integrated device.

The processor may include one or more processors, for example, including one or more Central Processing Units (CPUs). If the processor is one CPU, the CPU may be a single-core CPU or a multi-core CPU.

The memory is configured to store program codes and data of the game stage switching apparatus.

The processor is configured to invoke the program codes and data in the memory to execute the steps in the method embodiments above. Please refer to the descriptions in the foregoing method embodiments for details, and details are not described here again.