FIG. 3B illustrates an example of logic operations 350, again at a high level, for the controller 212 when no anomaly has occurred over some predetermined period, for example 10 ms. An interrupt signal may be generated periodically according to the predetermined period to wake the controller 212 (step 352). Since no anomaly (false short and true short) has caused the controller to wake over the predetermined period, the fact that no false positive and no short circuit events have occurred is “registered” (step 354) by decrementing the values of the counters that respectively track the numbers of false shorts and periodic shorts. The controller then goes back to sleep (step 356).

Note that the controller does not strictly have to sleep and then wake-up. In some embodiments, the controller may actively monitor the system line so that registration of a non-event (step 354) occurs at regular intervals in which short circuit events do not occur.

FIGS. 4A and 4B together are a flowchart 400 describing, in an exemplary embodiment, the operation of the controller in further detail.

In an aspect, most of the time the controller may typically be sleeping (step 401). The controller may wake up (step 403) upon at least two types of events that may occur, as determined at step 405.