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Method for dicing integrated fan-out packages without seal rings

專利號
US11177142B2
公開日期
2021-11-16
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.(TW Hsinchu)
發(fā)明人
Li-Hsien Huang; Yueh-Ting Lin; An-Jhih Su; Ming Shih Yeh; Der-Chyang Yeh
IPC分類
H01L21/56; H01L23/31; H01L25/16; H01L21/683; H01L23/00; H01L25/00
技術(shù)領(lǐng)域
die,dicing,conductive,molding,packages,in,pillars,dielectric,package,structure
地域: Hsinchu

摘要

A method includes attaching a first die and a second die to a carrier; forming a molding material between the first die and second die; and forming a redistribution structure over the first die, the second die and the molding material, the redistribution structure includes a first redistribution region; a second redistribution region; and a dicing region between the first redistribution region and the second redistribution region. The method further includes forming a first opening and a second opening in the dicing region, the first opening and the second opening extending through the redistribution structure and exposing the molding material; and separating the first die and the second die by cutting through a portion of the molding material aligned with the dicing region from a second side of the molding material toward the first side of the molding material, the second side opposing the first side.

說明書

A planarization process, such as chemical and mechanical polish (CMP), may optionally be performed to remove excess portions of the molding material 130 over the front side of the die 120. After the planarization process, the molding material 130, the conductive pillar 119, and the die connectors 128 have a coplanar upper surface, in some embodiments.

Referring next to FIG. 4, a redistribution structure 140 (may also be referred to as a front side redistribution structure) is formed over the molding material 130, the conductive pillar 119, and the die 120. The redistribution structure 140 comprises one or more layers of electrically conductive features (e.g., conductive lines 143, vias 145) formed in one or more dielectric layer (e.g., 142, 144, 146, and 148).

In some embodiments, the one or more dielectric layers (e.g., 142, 144, 146, and 148) are formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The one or more dielectric layers may be formed by a suitable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.

權(quán)利要求

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