As illustrated in FIG. 9, each of the semiconductor packages 160 (e.g., 160A, 160B) has a substrate 161 and one or more semiconductor dies 162 (e.g., memory dies) attached to an upper surface of the substrate 161. In some embodiments, the substrate 161 includes silicon, gallium arsenide, silicon on insulator (“SOI”) or other similar materials. In some embodiments, the substrate 161 is a multiple-layer circuit board. In some embodiments, the substrate 161 includes bismaleimide triazine (BT) resin, FR-4 (a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant), ceramic, glass, plastic, tape, film, or other supporting materials. The substrate 161 may include conductive features (e.g., conductive lines and vias, not shown) formed in/on the substrate 161. As illustrated in FIG. 9, the substrate 161 has conductive pads 163 formed on the upper surface and a lower surface of the substrate 161, which conductive pads 163 are electrically coupled to the conductive features of the substrate 161. The one or more semiconductor dies 162 are electrically coupled to the conductive pads 163 by, e.g., bonding wires 167. A molding material 165, which may comprise an epoxy, an organic polymer, a polymer, or the like, is formed over the substrate 161 and around the semiconductor dies 162. In some embodiments, the molding material 165 is conterminous with the substrate 161, as illustrated in FIG. 8.