FIG. 4 also illustrates a thinning of the encapsulant 401 in order to expose the vias 111, the first semiconductor device 201, and the second semiconductor device 301 for further processing. The thinning may be performed, e.g., using a mechanical grinding or chemical mechanical polishing (CMP) process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant 401, the first semiconductor device 201 and the second semiconductor device 301 until the vias 111, the first external connectors 209 (illustrated in FIG. 2), and the second external connectors 309 (illustrated in FIG. 3) have been exposed. As such, the first semiconductor device 201, the second semiconductor device 301, and the vias 111 may have a planar surface that is also planar with the encapsulant 401.
However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the encapsulant 401, the first semiconductor device 201, and the second semiconductor device 301 and expose the vias 111. For example, a series of chemical etches may be utilized. This process and any other suitable process may alternatively be utilized to thin the encapsulant 401, the first semiconductor device 201, and the second semiconductor device 301, and all such processes are fully intended to be included within the scope of the embodiments.