Once the first redistribution passivation layer 501 has been formed, first redistribution vias 503 may be formed through the first redistribution passivation layer 501 in order to make electrical connections to the first semiconductor device 201, the second semiconductor device 301, and the vias 111. In an embodiment the first redistribution vias 503 may be formed by using, e.g., damascene process whereby the first redistribution passivation layer 501 is initially patterned to form openings using, e.g., a photolithographic masking and etching process or, if the material of the first redistribution passivation layer 501 is photosensitive, exposing and developing the material of the first redistribution passivation layer 501. Once patterned, the openings are filled with a conductive material such as copper and any excess material is removed using, e.g., a planarization process such as chemical mechanical polishing. However, any suitable process or materials may be utilized.

After the first redistribution vias 503 have been formed, a first redistribution layer 505 is formed over an in electrical connection with the first redistribution vias 503. In an embodiment the first redistribution layer 505 may be formed by initially forming a seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first redistribution layer 505 is desired to be located.