Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates a formation of vias in accordance with some embodiments.
FIG. 2 illustrates a first semiconductor device in accordance with some embodiments.
FIG. 3 illustrates a placement of the first semiconductor device and a second semiconductor device in accordance with some embodiments.
FIG. 4 illustrates an encapsulation of the vias, the first semiconductor device, and the second semiconductor device in accordance with some embodiments.
FIGS. 5A-5B illustrate a formation of a redistribution structure in accordance with some embodiments.
FIG. 6 illustrates an optical lithography system for use in forming a redistribution structure in accordance with some embodiments.
FIGS. 7A-7D illustrate a pictographic view of portions of a redistribution structure in accordance with some embodiments.
FIG. 8A illustrates a graphical representation of the mean target thickness (THK) of a via relative to development time in accordance with some embodiments.
