Alternatively, the third substrate 701 may be an interposer used as an intermediate substrate to connect the third semiconductor device 703 and the fourth semiconductor device 705 to the vias 111. In this embodiment the third substrate 701 may be, e.g., a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. However, the third substrate 701 may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality. These and any other suitable materials may be used for the third substrate 701.

The third semiconductor device 703 may be a semiconductor device designed for an intended purpose such as being a logic die, a central processing unit (CPU) die, a memory die (e.g., a DRAM die), combinations of these, or the like. In an embodiment the third semiconductor device 703 comprises integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like, therein, as desired for a particular functionality. In an embodiment the third semiconductor device 703 is designed and manufactured to work in conjunction with or concurrently with the first semiconductor device 201.

The fourth semiconductor device 705 may be similar to the third semiconductor device 703. For example, the fourth semiconductor device 705 may be a semiconductor device designed for an intended purpose (e.g., a DRAM die) and comprising integrated circuit devices for a desired functionality. In an embodiment the fourth semiconductor device 705 is designed to work in conjunction with or concurrently with the first semiconductor device 201 and/or the third semiconductor device 703.