This application is a continuation of U.S. patent application Ser. No. 15/894,051, filed Feb. 12, 2018, which will issue as U.S. Pat. No. 10,276,431, which is a continuation of U.S. patent application Ser. No. 14/879,992 filed on Oct. 9, 2015, now issued U.S. Pat. No. 9,892,963, which is a divisional application of U.S. patent application Ser. No. 14/286,859 filed on May 23, 2014, now issued U.S. Pat. No. 9,159,666, which is a continuation-in-part of U.S. patent application Ser. No. 13/601,223 filed on Aug. 31, 2012, now issued U.S. Pat. No. 8,736,056, which in turn claims priority to U.S. Provisional Patent Application Ser. No. 61/677,862 filed on Jul. 31, 2012 and entitled “A Method of Reducing Contact Resistance of a Metal.” The entire disclosure of the above applications is incorporated herein by reference.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.