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Device and method for reducing contact resistance of a metal

專利號
US11177168B2
公開日期
2021-11-16
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Ya-Lien Lee; Hung-Wen Su; Kuei-Pin Lee; Yu-Hung Lin; Yu-Min Chang
IPC分類
H01L21/768; H01L23/532; H01L23/50; H01L21/285
技術領域
pvd,trench,tan,layer,ta,barrier,dielectric,ald,in,depositing
地域： Hsinchu

摘要

A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.

說明書

For example, as the critical dimension (CD) of devices are scaled down, any variations in the CD may become more relevant, including resulting variations in the contact resistance (Rc) of a metal structure in an IC device. Accordingly, what is needed is a method for further scaling down of the IC device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purpose only. In fact, the dimension of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross sectional view of a device according to one or more embodiments of the present disclosure.

FIG. 2 is a flow chart of a method of fabricating a device for implementing one or more embodiments of the present disclosure.

FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are cross sectional views of forming a device for implementing one or more embodiments of the present disclosure.

FIG. 15 is an example of a contact resistance improvement for the devices of FIG. 1 and FIGS. 3-14.

FIG. 16 provides graphs of different element ratios for the devices of FIG. 1 and FIGS. 3-14.

權利要求

1
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