An interlayer dielectric (ILD) layer 36 is disposed over the S/D epitaxial layer 40 and a conductive contact layer 60 is disposed on the S/D epitaxial layer 40 and a conductive plug 65 passing though the ILD layer 36 is disposed over the conductive contact layer 60. The conductive contact layer 60 includes one or more layers of conductive material. In some embodiments, the conductive contact layer 60 includes a silicide layer, such as WSi, NiSi, TiSi or CoSi or other suitable silicide material.

The first GAA FET Q1 and the second GAA FET Q2 have substantially the same structure except for the source/drain regions. As shown in FIG. 1, the source/drain epitaxial layer 40 of the first GAA FET Q1 is in physical and electrical contact with all of the semiconductor wires 25, while the source/drain epitaxial layer 40 of the second GAA FET Q2 is in physical and electrical contact with only some of the semiconductor wires 25. In some embodiments, as shown in FIG. 1, the source/drain epitaxial layer 40 of the second GAA FET Q2 is in physical and electrical contact with two of the four semiconductor wires 25. In other words, at least one of the semiconductor wires 25 of the second GAA FET Q2 is electrically separated from the source/drain epitaxial layer 40 disposed thereabove, by the dielectric layer 35.