FIGS. 2-21D show various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 2-21D, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to FIG. 1 may be employed in the embodiment of FIGS. 2-21D, and detailed explanation thereof may be omitted. General methods of manufacturing a GAA FET can be found in U.S. patent application Ser. No. 15/157,139, application Ser. No. 15/064,402 and/or application Ser. No. 15,098,073, the entire contents of each of which are incorporated herein by reference.
As shown in FIG. 2, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region. The ion implantation is performed to prevent a punch-through effect. The substrate 10 may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants 12 are, for example boron (BF2) for an n-type Fin FET and phosphorus for a p-type Fin FET.
Then, as shown in FIG. 3, stacked semiconductor layers are formed over the substrate 10. The stacked semiconductor layers include first semiconductor layers 20 and second semiconductor layers 25. Further, a mask layer 16 is formed over the stacked layers.
