After the dielectric layer 35 is formed, the source/drain region is etched to form a second S/D space 22, as shown in FIGS. 12A-12D. Depending on the desired drive current (or resistance), the depth of the second S/D space 22 is adjusted. For example, in the case of FIG. 12A, the dielectric layer 35 and only the uppermost second semiconductor layer 25 are etched, while the remaining second semiconductor layers 25 remain embedded in the dielectric layer 35. In the case of FIG. 12B, two upper second semiconductor layers 25 and the dielectric layer 35 are etched to expose end portions of the two upper second semiconductor layers 25 in the second S/D space 22. Similarly, in the case of FIG. 12C, three second semiconductor layers 25 from the top and the dielectric layer 35 are etched to expose end portions of the three second semiconductor layers 25 in the second S/D space 22. In the case of FIG. 12D, the dielectric layer 35 and the second semiconductor layers 25 are etched so that end portions of all of the second semiconductor layers 25 are exposed in the second S/D space 22. In some embodiments, all of the structures shown in FIGS. 12A-12D are provided on the same substrate 10 (on one semiconductor chip). In other embodiments, only some of the structures shown in FIGS. 12A-12D are provided on the same substrate 10. The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations.