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Method of manufacturing a semiconductor device and a semiconductor device

專利號
US11177179B2
公開日期
2021-11-16
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.(TW Hsinchu)
發(fā)明人
Hung-Li Chiang; Chao-Ching Cheng; Chih-Liang Chen; Tzu-Chiang Chen; Ta-Pen Guo; Yu-Lin Yang; I-Sheng Chen; Szu-Wei Huang
IPC分類
H01L21/8234; H01L29/66; H01L29/06; H01L27/088; G03F1/38; H01L21/308; H01L29/423; B82Y10/00; H01L29/08; H01L29/78; H01L29/775; H01L29/417; H01L29/786; H01L27/092; H01L21/8238
技術(shù)領(lǐng)域
layer,epitaxial,fet,drain,gaa,layers,gate,dielectric,in,fin
地域: Hsinchu

摘要

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

說明書

FIG. 14 shows the one or more lithography and etching operations to fabricate the structures shown in FIGS. 13A-13F on the same substrate, according to some embodiments. To fabricate all of the structures shown in FIGS. 13A-13F, at most three lithography/etching operations can be performed. For example, the first, third and fifth S/D regions for a one-wire contact structure, a three-wire contact structure and a five-wire contact structure, respectively, are subjected to a first etching operation to a depth of D, which corresponds to an etching depth to cut and expose ends of the uppermost second semiconductor layer 25, but not reach the next second semiconductor layer 25. The second, fourth and sixth S/D regions for a two-wire contact structure, a four-wire contact structure and a six-wire contact structure, respectively, are covered by, for example, photoresist formed by a lithography operation. Then, the second, third and sixth S/D regions are subjected to a second etching operation to a depth of 2D, while the first, fourth and fifth S/D regions are covered. Further, the fourth, fifth and sixth S/D regions are subjected to a third etching operation to a depth of 3D, while the first, second and third S/D regions are covered. The order of the first to third etching operations can be any order.

權(quán)利要求

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