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Method of manufacturing a semiconductor device and a semiconductor device

專利號(hào)
US11177179B2
公開日期
2021-11-16
申請(qǐng)人
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.（TW Hsinchu）
發(fā)明人
Hung-Li Chiang; Chao-Ching Cheng; Chih-Liang Chen; Tzu-Chiang Chen; Ta-Pen Guo; Yu-Lin Yang; I-Sheng Chen; Szu-Wei Huang
IPC分類
H01L21/8234; H01L29/66; H01L29/06; H01L27/088; G03F1/38; H01L21/308; H01L29/423; B82Y10/00; H01L29/08; H01L29/78; H01L29/775; H01L29/417; H01L29/786; H01L27/092; H01L21/8238
技術(shù)領(lǐng)域
layer,epitaxial,fet,drain,gaa,layers,gate,dielectric,in,fin
地域： Hsinchu

摘要

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

說明書

FIG. 11 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIGS. 12A, 12B, 12C and 12D show one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIGS. 13A, 13B, 13C, 13D, 13E and 13F show one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIG. 14 shows various etching operations for manufacturing structures shown in FIGS. 13A-13F.

FIG. 15 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIG. 16 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIG. 17 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIG. 18 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

FIG. 19 shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure.

權(quán)利要求

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