According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the source/drain region, thereby covering the exposed second semiconductor layers. The dielectric layer is etched, thereby forming a second source/drain space, at least one of the second semiconductor layers being exposed in and crossing the second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers exposed in the second source/drain space is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer disposed thereabove by the dielectric layer. In one or more of the foregoing or following embodiments, the dielectric layer includes a low-k dielectric material. In one or more of the foregoing or following embodiments, after the source/drain epitaxial layer is formed, the sacrificial gate structure is removed, thereby exposing a part of the fin structure, the first semiconductor layers are removed from the exposed fin structure, thereby forming channel layers including the second semiconductor layers, and a gate dielectric layer and a gate electrode layer are formed around the channel layers. In one or more of the foregoing or following embodiments, the gate electrode layer wraps around the at least one of the second semiconductor layers separated from the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the at least one of the second semiconductor layers separated from the source/drain epitaxial layer is located closer to a substrate than remaining second semiconductor layer contacting the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, two or more of the second semiconductor layers are separated from the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, only one of the second semiconductor layers is in contact with the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first semiconductor layers are made of SiGe, and the second semiconductor layers are made of Si.